Emerging Challenges of Signal Integrity Issues and High-Speed Interconnects

IEEE Electronic Packaging Society Distinguished Lecture With the increasing demands for higher signal speeds coupled with the need for decreasing feature sizes, signal integrity effects such as delay, distortion, reflections, crosstalk, ground bounce and electromagnetic interference have become the dominant factors limiting the performance of high-speed systems. These effects can be diverse and can seriously impact the design performance at all hierarchical levels including integrated circuits, printed circuit boards, multi-chip modules and backplanes. If not considered during the design stage, signal and power integrity effects can cause failed designs. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in high-speed designs. Consequently, preserving signal integrity has become one of the most challenging tasks facing designers of modern multifunction and miniature electronic circuits and systems. This talk provides a comprehensive approach for understanding the multidisciplinary problem of signal and power integrity: issues/modeling/analysis in high-speed designs. Speaker(s): Prof. Ram Achar Agenda: 6:30 PM : Announcements and Introduction of Speaker 6:40 PM – Talk 7:20 PM – Q and A Room: Meeting Room, Bldg: Patrick Henry Library, 101 Maple Ave E, Vienna, Virginia, United States, Virtual: https://events.vtools.ieee.org/m/365848