Abstract: The recently developed Intel Loihi Spiking Neural Network Manycore Processor is an asynchronous computing system that performs computations based on the presence of voltage spikes. This design is extremely efficient because significant power is only consumed when spikes are propagating through the processor cores. This work discusses two algorithms for AI and autonomous decision making that have been implemented in a spiking neural network format including: M by N asset allocation and constraint satisfaction.

Even after acceleration on a high performance server based computing system enhanced with a high end graphics processing unit (GPU), algorithms for solution searching do not scale well for real time use on large problem sizes. Thus, to enable real time use of allocation problems, particularly in power constrained environments (such as autonomous air vehicles), alternative implementations of the agent logic are needed, such as the proposed SNN approach. This work enables allocation algorithms to operate in portable and edge computing systems at extreme low power and computation efficiency.

Furthermore, we show that constraint satisfaction problems (CSPs) can be solved quickly and efficiently using spiking neural networks. Constraint satisfaction is a general problem solving technique that can be applied to a large number of different applications. To demonstrate the validity of this algorithm, we show successful execution of the Boolean satisfiability problem (SAT) on the Intel Loihi spiking neuromorphic research processor. In many cases, constraint satisfaction problems have solution sets as opposed to single solutions. Therefore, the manycore architecture of the Loihi chip is used to parallelize the solution finding process, leading to a quasi-complete solution set. We show that embedded spiking neuromorphic hardware is capable parallelizing the constraint satisfaction problem solving process to yield extreme gains in terms of time, power, and energy.

Bio: Dr. Chris Yakopcic is currently on the research faculty at the University of Dayton. He received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from the University of Dayton in 2009, 2011, and 2014 respectively. His current research includes memristor device modelling, analogue circuit design with memristor devices, and implementing neuromorphic algorithms on memristor crossbars. He now also works on developing algorithms for spiking neural network processors, and porting deep learning to low power embedded systems. In 2013 he was awarded the IEEE / INNS International Joint Conference on Neural Networks best paper award for a paper on memristor device modelling. For 2019, Chris was chosen as the IEEE Dayton Section Computer Society Award winner for his work on memristor based electronic systems for extreme low-power computation and cutting edge algorithms for autonomous systems.

Speaker(s): Dr. Chris Yakopcic,

Dayton, Ohio, United States, Virtual: https://events.vtools.ieee.org/m/295622